The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a semiconductor device having an upper/lower channel.
Recently, reduction in semiconductor device design rule has led to a decrease in dimension of a unit memory cell.
In order to cope with the decrease in the dimension of a unit memory cell, a transistor having an upper/lower channel formed by vertically arranging the source and drain in an active region is introduced.
FIG. 1A is a cross-sectional view of a typical upper/lower transistor array and FIG. 1B is a top view of the typical upper/lower transistor array. In FIG. 1B, a line pattern and a gate pattern in FIG. 1A are enlarged.
Referring to FIGS. 1A and 1B, the upper/lower transistor array includes a plurality of transistors with an upper/lower channel. Each transistor includes a pillar pattern 11 and a gate pattern 12 formed on sidewalls of the pillar pattern 11. The gate pattern 12 includes a gate insulation layer 12B and a gate electrode 12A. Also, the transistor includes a source and a drain formed in upper and lower portions of the pillar pattern 11. The source 14A and drain 14B formed in the lower portion of the pillar pattern 11 functions as a line, which connects the gate pattern 12 and a line pattern 13.
The line pattern 13 has a first linewidth CD1. The first linewidth CD1 is fixed by the design rule. Likewise, a linewidth of the pillar pattern 11 defining a width of the transistor is fixed due to a limitation in the photo-exposure technology. That is, when a develop inspection critical dimension (DICD) of a photoresist pattern is 50 nm or less, the photoresist pattern collapses.
FIG. 2 is an electron microscopic picture of a collapsed photoresist pattern.
Referring to FIG. 2, when a develop inspection critical dimension (DICD) of a photoresist pattern is 50 nm or less, the photoresist pattern collapses. Thus, the width of the photoresist pattern 21 is limited. Therefore, the width of the pillar pattern 11 and the width of the gate pattern 12 are substantially the same since the width of the pillar pattern 11 is limited by the width of the gate pattern 12.
Referring to FIG. 1B, the line pattern 13 is not formed in a line due to the above process condition. A gate electrode 12A of the gate pattern 12 is formed between the line patterns 13 and the gate electrode 12A functions as a wordline. Generally, when the conductive material is formed in a line, it can have minimum resistance. For instance, a planar type wordline is formed to have one conductive pattern. Thus, it is possible to secure the minimal resistance.
However, in the upper/lower channel transistor, the line pattern 13 and gate electrode 12A are not formed in one conductive material. Thus, the resistance increases. Driving voltage of the transistor is applied to the wordline.
FIG. 3 is a top view of the wordline.
Referring to FIG. 3, the wordline 31 has a third linewidth CD3. The third linewidth CD3 is the width of the gate electrode 12A.
Since resistance of a line is inverse proportional to its surface area, the wordline 31 with a third linewidth CD3 will decrease the transmission efficiency of the driving voltage when it is applied to a transistor.
The wordline 31 has a stack structure having a metal layer and a polysilicon layer having higher resistance than the metal layer, which further increases the resistance of the wordline 31. Further, the contact resistance is increased due to the insufficiency in the contact area between the line pattern 13 and the gate electrode 12A. The increase in the contact resistance has contributed to the overall increase in the resistance in the wordline 31.
As a result, the transmission efficiency of the driving voltage of each transistor in the transistor array decreases, thereby decreasing reliability and stability of the device.